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This article presents a back-off efficient power amplifier (PA) for mm-wave 5G and upcoming 6G beamforming phased array transceivers (PATs), incorporating advanced circuit designs and novel implementations in both passive and active components. Conventional back-off efficient PAs in the mm-wave frequency range occupy a large chip area, making it hard to fit them into PATs. To overcome this issue, we propose a compact back-off efficient Doherty PA (DPA) with a common base (CB) structure as the core of the PA and small low-loss passive elements. In addition, the proposed architecture moves the role of the input hybrid coupler to the interstage matching network while maintaining DPA functionality. The interstage matching provides the required phases for the main and auxiliary PAs, power division, and impedance matching. The PA prototype is fabricated in the GlobalFoundries 90-nm BiCMOS (9 HP) process. It achieves a peak gain of 20.4 dB at 28.45 GHz with a 1-dB bandwidth of 4.45 GHz. Under large-signal conditions, it archives >19.5-dBm Psat with >36% PAEsat. Its P1dB at 26, 28, and 30 GHz are 19.4, 19.3, and 19.3 dBm with 38.5%, 37.3%, and 36.8% PAE1 dB, respectively. In the 6-dB power back-off region, it reaches efficiencies of 29.1%, 31.1%, and 29.3% at 26, 28, and 30 GHz, respectively. When tested with the NR-FR2 test model at these frequencies, the PA achieves Pavg of 8.25, 8.45, and 8 dBm, and PAEavg of 13.9%, 14.5%, and 13.7% for a 400 M 1-CC 64-QAM signal, maintaining an rms error vector magnitude (EVMrms) of −25.8, −25.8, and −25.7 dB. In addition, in adjacent channel power ratio (ACPR) tests, the PA achieves −27, −26.2, and −30.8 dBc on the lower side and −28.4, −28.5, and −27.6 dBc on the higher side channels at 26, 28, and 30 GHz, respectivelyNot Available